This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-336606, filed Nov. 26, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory device composed of transistors and capacitors and a method of manufacture the same.
In recent years, with increasing packing density of semiconductor integrated circuits, the minimum processing dimensions and the memory cell area keep on shrinking. The area of the capacitor in each memory cell has become increasingly reduced accordingly. A decrease in the memory cell area results in a decrease in the capacitance of the memory cell capacitor (storage capacitance Cs). The storage capacitance is required to have a value larger than a constant value in terms of sensitivity, soft errors, circuit noise, etc. To solve this problem, two methods have been considered: one to increase the storage capacitance by forming the capacitor in three-dimensions to thereby maximize the capacitor surface area, and one to use an insulating film high in permittivity (highly dielectric film) for the capacitor insulating film.
With the generation of design rules of 0.15 xcexcm or less (the generation of 512-Mb DRAMs and later), the processing of three-dimensional shaped, complex storage node electrodes involves fine-pattern processing and is therefore getting more and more difficult. To increase the storage capacitance, therefore, it has become increasingly important to form storage capacitors in the three-dimensional form and use a high-permittivity insulating film for the capacitor insulating film.
A typical example of the high-permittivity insulating film is a film of (Ba, Sr)TiO3 (hereinafter referred to as a BST film). In the use of a BST film, the use of an Ru film or a composite film of RuO2/Ru for storage node electrodes has been considered (S. Yamauchi et al., IDEM Technical Digest, 1995, pp. 119-122). The Ru film exhibits conductivity even if it is oxidized in the middle of the process because of the use of an oxygen atmosphere in the middle of the formation of the BST film.
Reference is now made to FIG. 7 to describe the stacked DRAM capacitor structure using the composite film of RuO2/Ru as the storage node electrode. After a device isolation layer 12 is formed on a p-type Si substrate 11, a gate insulating film 13, gate electrodes (word lines) 14, a gate capping layer 15, source/drain diffusion layers 16, and a silicon nitride film 17 are formed. A first interlayer insulating film 15 is deposited, then planarized and patterned. After that, plugs 19 and 20 made of polysilicon are buried in regions of storage node electrode contacts and bit line contacts. Later, a second interlayer insulating film 152 is formed and a bit line (BL) 154 is formed on the film 152 so as to connect to the plug 19 through the contact plug 153. After a third interlayer insulating film 155 is deposited, the surface is planarized and storage node electrode contact holes are formed. Storage node electrode contact plugs 156 which maid of nxe2x88x92 type polysilicon are formed in the contact holes. After that, a film of storage node electrode material is formed and then patterned by means of standard photolithographic metal masking and etching techniques using resist to form storage node electrodes 29. After the resist is removed, a capacitor insulating film 31 made of a highly dielectric material, such as a BST film, is formed and then a plate electrode 32 is formed.
In such a memory cell structure, the BL contact plugs and the SN contact plugs are formed separately. In such a case, because the SN contact plugs are placed between the bit lines defined under the minimum design rules, they have to be reduced in size, which will lead to a significant increase in their resistance. For this reason, the speed at which each memory cell is written into or read from may become so unsettled as to affect the cell operation.
It is an object of the present invention to provide a semiconductor memory device and a method of manufacture thereof which permit SN contact plugs to be prevented from increasing in resistance to stabilize the speed at which memory cells are written into or read from.
According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a transistor having a gate electrode formed above a semiconductor substrate and source and drain regions formed in the semiconductor substrate; an interlayer insulating film formed to cover the transistor and having contact holes that lead to the source and drain regions, respectively; a bit line contact formed in one of the contact holes; a storage node electrode contact formed in the other of the contact holes; a bit line contact plug formed on the bit line contact; a storage node electrode contact plug formed on the storage node electrode contact; a bit line formed to connect to the bit line contact plug; and a capacitor storage node electrode formed to connect to the storage node electrode contact plug, and wherein each of the bit line contact plug and the storage node electrode contact plug has a barrier metal layer formed on its associated contact and a metal layer formed on the barrier metal layer, and the barrier metal layer is formed on only the bottom surface of the metal layer.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device comprising: a transistor having a gate electrode formed above a semiconductor substrate and source and drain regions formed in the semiconductor substrate; an interlayer insulating film formed to cover the transistor and having contact holes that lead to the source and drain regions, respectively; a bit line contact plug formed on the interlayer insulating film and electrically connected to one of the source and drain regions; a bit line formed to connect to the bit line contact plug; a storage node electrode contact plug formed on the interlayer insulating film and electrically connected to the other of the source and drain regions; and a capacitor storage node electrode formed to connect to the storage node electrode contact plug, characterized by forming the bit line contact plug and the storage node electrode contact plug simultaneously.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device comprising the steps of: forming a transistor having a gate electrode and source and drain regions in a semiconductor substrate; forming a first interlayer insulating film to cover the transistor above the semiconductor substrate; forming contact holes in the first interlayer insulating film which lead to the source and drain regions, respectively; forming a contact in each of the contact holes; depositing a barrier metal film and a metal film in sequence on the first interlayer insulating film; patterning the barrier metal film and the metal film to form a bit line contact plug and a storage node electrode contact plug, the bit line contact plug being electrically connected to one of the source and drain regions and the storage node electrode contact plug being electrically connected to the other of the source and drain regions; forming an insulating film on the sidewall of each of the bit line contact plug and the storage node electrode contact plug; forming a second interlayer insulating film on the first interlayer insulating film to isolate the bit line contact plug and the storage node electrode contact plug from each other; forming a trench in the second interlayer insulating film which leads to the bit line contact plug; forming a bit line in the trench; forming an insulating film on the top of the bit line; forming a storage node electrode on the second interlayer insulating film which connects to the storage node electrode contact plug; forming a dielectric film to cover the top of the storage node electrode; and forming an upper electrode to cover the top of the dielectric film.
The present invention provides the following advantages:
In the SN contact plug, since the barrier metal layer of high resistivity is formed on only the bottom surface of the metal layer in a self-aligned manner, the manufacturing process can be simplified and the resistance of the plug can be reduced.
The manufacturing process can be simplified by forming the bit line contact plug and the SN electrode contact plug simultaneously.
Since the SN contact plug is formed prior to the formation of the bit line, the shape of the SN contact can be formed without being affected by variations in the processing of the bit line and the SN contact plug of low resistivity can be formed stably.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.